1. Technical Field
This invention relates to driver circuits for integrated circuit chips, and more particularly to a CMOS driver circuit for producing outputs from an integrated circuit device to off-chip environments where overvoltages may occur, and where simultaneous switching noise is a concern.
2. Description of the Related Art
A computer system requires a number of integrated circuit devices such as microprocessor or memory chips to be connected to high performance bus architectures, many of which encompass multi-voltage environments. These environments may introduce bus over-voltages that exceed the reliability specification for the driver circuits used at the output pads of the microprocessor or memory I/C's, especially if the IC's are designed in a low-voltage technology, e.g., 3 V power supply devices.
One of the most widely used techniques for preventing overvoltage damage to a CMOS output driver is taught in U.S. Pat. No. 5,151,619, where a circuit is shown which uses an N-well containing a transistor shunting the gate and drain of the P-channel pull-up transistor, so that this gate follows the output node if it goes above the supply. The N-well is sourced through a transistor, instead of directly from the supply.
Another example of integrated circuit chip technology wherein voltage supplies are of mixed values is disclosed by M. Ueda, et al, in "A 3.3 V ASIC for Mixed Voltage Applications With Shut Down Mode," Custom Integrated Circuits Conference, May 1993, pages 25.5.1-25.5.4.
A factor in the design of a CMOS output driver is the effect of lead inductance in the package. The connections from the output pads of an integrated circuit chip to the leads of the package itself tend to act as inductive elements, and will introduce noise by bumping the ground voltage and supply voltage at times of rapid transition between one and zero levels. Previous attempts to deal with this factor have included a compensating circuit which prevents the transition from being too rapid, yet does not unduly compromise the speed of the circuit. This type of compensating circuit must be reconciled with the possibility of overvoltage on the output node, however.